A phase-change memory is a device that operates using a phase-change layer formed of a chalcogenide material, which has an electrical resistance that varies according to its phase. In the typical phase-change memory, Joule heating is used as a heating source to cause a change in phase. FIG. 1 shows a conventional phase-change memory cell array.
As shown in FIG. 1, a conventional phase-change memory cell typically includes a cell transistor CTR having a gate connected to a word line WL as well as a phase-change memory cell PCC and a resistor R that are connected in series between a drain of the cell transistor CTR and a bit line BL. If a word line WL and a bit line BL are selected, current is applied to a selected phase-change memory cell PCC corresponding to the selected word line WL and bit line BL to change the phase of the phase-change memory cell PCC.
FIG. 2A illustrates the principle of operation of the conventional phase-change memory. Referring to FIG. 2A, a high current pulse of about 2 mA to 3 mA is applied through a contact 10 to a phase-change layer 20 for several microseconds to heat the phase-change layer 20 to a melting temperature Tm. By rapidly cooling the phase-change layer 20 immediately after interrupting the current pulse, a high-resistance wholly amorphous programming region 30 is formed at a contact portion between the phase-change layer 20 and the contact 10. In this case, the phase-change memory cell is in a “reset” state, which is defined as, for example, storage of data “1.”
If a current pulse of about 1 mA to 2 mA is passed through the contact 10 to the phase-change layer 20 for several microseconds and then immediately cooled again, the wholly amorphous programming region 30 crystallizes and the resistance of the phase-change layer 20 decreases again. In this case, the phase-change memory cell is in a “set” state, which is defined as, for example, storage of data “0.”
FIG. 2B is a graph of resistance versus current for the phase-change memory cell of FIG. 2A. That is, current applied to the phase-change layer 20 is increased to about 0.4 mA to about 0.38 mA, and a variation in the resistance of the phase-change layer is measured. Referring to FIG. 2B, curve (a) represents the situation where the phase-change memory cell was initially in the reset state with a reset resistance Rreset of about 300 kΩ. When the current reached 1 mA to 2 mA, the resistance markedly reduced to about 3 kΩ. Accordingly, the phase-change memory cell transited from the reset state to the set state in the current range of 1 mA to 2 mA. Thus, a set resistance Rset is about 3 kΩ and a set current Iset, which makes the transition to the set state, is about 1 mA to 2 mA. Curve (b) represents the case where the phase-change memory cell was initially in the set state with the set resistance Rset. The resistance increases to about 300 kΩ when the current increased from about 2 mA to 3 mA. Accordingly, the phase-change memory cell transited from the set state to the reset state. Ireset is about 2 mA to 3 mA.
To read stored data, a current, which is less than the current Ireset and Iset, is supplied or a voltage is applied to the phase-change memory cell and then a variation in resistance is detected. As shown in FIG. 2B, a switching ratio of the reset resistance to the set resistance may be 100 or more. In the conventional phase-change memory, application of a high current Ireset or Iset of several milliamperes is required for the transition to a wholly amorphous state or a crystalline state, respectively, and data can be read or stored using the larger variation in the resistance resulting from the phase transition. In this case, the current required may be large enough to cause overheating in a cell transistor, which may be a serious obstacle in producing highly integrated memory devices.
Also, for the conventional phase-change memory, it typically takes a period of about several microseconds to transit to the reset or set state, thereby slowing down the operating speed of the phase-change memory.